Bits on AVR

Memory
The ATMega memory consists of three parts:
● Data memory of SRAM : used for temporary storage of data values
● Program memory, which is a Flash Memory, that can be rewritten up to 10,000 times
● Finally the EEPROM memory, which is used for permanent storage of data values or initial parameters for the microcontroller.
In-System Programmable flash
--can easily program chips, even while in-circuit.
Many peripherals:
a whole bunch of internal and external interrupt sources and peripherals are available on a wide range of devices (timers, UARTs, ADC, watchdog,etc.).
32 registers:
The 32 working registers (all directly usable by the ALU) help keep performance snappy, reducing the use of time consuming RAM access.
Internal RC oscillators can be used on many chips to reduce part count further.
Flexible interrupt module with multiple internal/ external interrupt sources.
Multiple power saving modes.

AVR Microcontroller and C language

High Level Languages (HLLs) are rapidly becoming the standard methodology for

embedded microcontrollers due to improved time-to-market and simplified

maintenance support. In order to ensure that the new ATMEL AVR family of

microcontrollers was well suited as a target for C compiler, the external C compiler

development was started before the AVR architecture and instruction set were

completed. During the initial development of the C compiler, several potential

improvements in the AVR were identified and implemented. The result of this

cooperation between the compiler developer and the AVR development team is a

microcontroller for which highly efficient, high performance code is generated.

The AVR Microcontroller

The AVR enhanced RISC microcontrollers are based on a new RISC architecture

that has been developed to take advantage of semiconductor integration and software

capabilities of the 1990's. A block diagram of the AVR architecture is given in figure 1.

The memory sizes and peripherals indicated in the figure are for the AT90S8414

microcontroller.

Central in the AVR architecture is the fast-access RISC register file, which consists of

32 x 8-bit general purpose working registers. Within one single clock cycle, AVR can

feed two arbitrary registers from the register file to the ALU, do a requested operation,

and write back the result to an arbitrary register. The ALU supports arithmetic and

logic functions between registers or between a register and a constant. Single register

operations are also executed in the ALU.

As can be seen from the figure, AVR uses a Harvard architecture, where the program

memory space is separated from the data memory space. Program memory is accessed

with a single level pipelining. While one instruction is being executed, the next

instruction is being pre-fetched from the program memory.

Due to the true single cycle execution of arithmetic and logic operations, the AVR

microcontrollers achieve performance approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

The Architecture allows for up to 8M Bytes program memory, and 16MBytes of Data

memory, and covers a wide range of applications.